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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad9221/ad9223/ad9220 complete 12-bit 1.5/3.0/10.0 msps monolithic a/d converters features monolithic 12-bit a/d converter product family family members are: ad9221, ad9223, and ad9220 flexible sampling rates: 1.5 msps, 3.0 msps, and 10.0 msps low power dissipation: 59 mw, 100 mw, and 250 mw single 5 v supply integral nonlinearity error: 0.5 lsb differential nonlinearity error: 0.3 lsb input referred noise: 0.09 lsb complete on-chip sample-and-hold amplifier and voltage reference signal-to-noise and distortion ratio: 70 db spurious-free dynamic range: 86 db out-of-range indicator straight binary output data 28-lead soic and 28-lead ssop functional block diagram vina capt capb sense otr bit 1 (msb) bit 12 (lsb) vref dvss avss cml ad9221/ad9223/ad9220 sha digital correction logic output buffers vinb 1v refcom 5 5 4 4 3 3 3 12 dvdd avdd clk mode select mdac3 gain = 4 mdac2 gain = 8 mdac1 gain = 16 a/d a/d a/d a/d general description the ad9221, ad9223, and ad9220 are a generation of high performance, single supply 12-bit analog-to-digital converters. each device exhibits true 12-bit linearity and temperature drift performance 1 as well as 11.5-bit or better ac performance. 2 the ad9221/ad9223/ad9220 share the same interface options, package, and pinout. thus, the product family provides an upward or downward component selection path based on performance, sample rate and power. the devices differ with respect to their specified sampling rate, and power consumption, which is re flected in their dynamic performance over frequency. the ad9221/ad9223/ad9220 combine a low cost, high speed cmos process and a novel architecture to achieve the resolution and speed of existing hybrid and monolithic implementations at a fraction of the power consumption and cost. each device is a complete, monolithic adc with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. an external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the applica tion. the devices use a multistage differential pipelined architecture with digital output error correction logic to provide 12-bit accu- racy at the specified data rates and to guarantee no missing codes over the full operating temperature range. the input of the ad9221/ad9223/ad9220 is highly flexible, allowing for easy interfacing to imaging, communications, medi- cal, and data-acquisition systems. a truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. the sample-and-hold ampli fier (sha) is equally suited for both multiplexed sys- tems that sw itch full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the nyquist rate. also, the ad9221/ad9223/ad9220 is well suited for communication systems employing direct- if down conversion since the sha in the differential input mode can achieve excellent dynamic performance far beyond its specified nyquist frequency. 2 a single clock input is used to control all internal conversion cycles. the digital output data is presented in straight binary output format. an out-of-range (otr) signal indicates an over- flow condition that can be used with the most significant bit to determine low or high overflow. product highlights the ad9221/ad9223/ad9220 family offers a complete single- chip sampling 12-bit, analog-to-digital conversion function in pin compatible 28-lead soic and ssop packages. flexible sampling rates?he ad9221, ad9223, and ad9220 offer sampling rates of 1.5 msps, 3.0 msps, and 10.0 msps, respectively. low power and single supply?he ad9221, ad9223, and ad9220 consume only 59 mw, 100 mw, and 250 mw, respec- tively, on a single 5 v power supply. excellent dc performance over temperature?he ad9221/ ad9223/ad9220 provide 12-bit linearity and temperature drift performance. 1 excellent ac performance and low noise?he ad9221/ ad9223/ad9220 provide better than 11.3 enob performance and have an input referred noise of 0.09 lsb rms. 2 flexible analog input range?he versatile on-board sample- and-hold (sha) can be configured for either single-ended or differential inputs of varying input spans. notes 1 excluding internal voltage reference. 2 depends on the analog input configuration.
rev. e e2e ad9221/ad9223/ad9220especifications (avdd = 5 v, dvdd = 5 v, f sample = max conversion rate, v ref = 2.5 v, vinb = 2.5 v, t min to t max , unless otherwise noted.) parameter ad9221 ad9223 ad9220 unit resolution 12 12 12 bits min max conversion rate 1.5 3 10 mhz min input referred noise (typ) v ref = 1 v 0.23 0.23 0.23 lsb rms typ v ref = 2.5 v 0.09 0.09 0.09 lsb rms typ accuracy integral nonlinearity (inl) () ( ) ( ) ( ) (+ ) ( = ) ( = ) ( ) ( ) ( ) ( ) ( ) ? ( ) < = ( )
rev. e ad9221/ad9223/ad9220 e3e ac specifications (avdd = 5 v, dvdd= 5 v, f sample = max conversion rate, v ref = 1.0 v, vinb = 2.5 v, dc coupled/single- ended input t min to t max , unless otherwise noted.) parameter ad9221 ad9223 ad9220 unit max conversion rate 1.5 3.0 10.0 mhz min dynamic performance input test frequency 1 (vina = e0.5 dbfs) 100 500 1000 khz signal-to-noise and distortion (sinad) 70.0 70.0 70 db typ 69.0 68.5 68.5 db min effective number of bits (enobs) 11.3 11.3 11.3 db typ 11.2 11.1 11.1 db min signal-to-noise ratio (snr) 70.2 70.0 70.2 db typ 69.0 68.5 69.0 db min total harmonic distortion (thd) e83.4 e83.4 e83.7 db typ e77.5 e76.0 e76.0 db max spurious free dynamic range (sfdr) 86.0 87.5 88.0 db typ 79.0 77.5 77.5 db max input test frequency 2 (vina = e0.5 dbfs) 0.50 1.50 5.0 mhz signal-to-noise and distortion (sinad) 69.9 69.4 67.0 db typ 69.0 68.0 65.0 db min effective number of bits (enobs) 11.3 11.2 10.8 db typ 11.2 11.1 10.5 db min signal-to-noise ratio (snr) 70.1 69.7 68.8 db typ 69.0 68.5 67.5 db min total harmonic distortion (thd) e83.4 e82.9 e72.0 db typ e77.5 e75.0 e68.0 db max spurious free dynamic range (sfdr) 86.0 85.7 75.0 db typ 79.0 76.0 69.0 db max full power bandwidth 25 40 60 mhz typ small signal bandwidth 25 40 60 mhz typ aperture delay 111ns typ aperture jitter 444ps rms typ acquisition to full-scale step 125 43 30 ns typ specifications subject to change without notice. digital specifications (avdd = 5 v, dvdd = 5 v, t min to t max , unless otherwise noted.) parameter symbol unit clock input high level input voltage v ih 3.5 v min low level input voltage v il 1.0 v max high level input current (v in = dvdd) i ih ( = ) = ( = ) ( = ) ( = ) ( = ) = ( = ) ( = ) ( = ) ( = )
rev. e e4e ad9221/ad9223/ad9220 switching specifications (t min to t max with avdd = 5 v, dvdd = 5 v, c l = 20 pf) parameter symbol ad9221 ad9223 ad9220 unit clock period * t c 667 333 100 ns min clock pulsewidth high t ch 300 150 45 ns min clock pulsewidth low t cl 300 150 45 ns min output delay t od 888ns min 13 13 13 ns typ 19 19 19 ns max pipeline delay (latency) 333c lock cycles * the clock period may be extended to 1 ms without degradation in specified performance @ 25 + + + + + + + + + + + + ( ) ja = 71.4 jc = 23 ja = 63.3 jc = 23 + + + + + + ( )
rev. e ad9221/ad9223/ad9220 e5e pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9221/ ad9223/ ad9220 clk avss avdd dvss dvdd ( lsb) bit 12 bit 11 bit 10 cml vina vinb bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 refcom capb capt bit 3 bit 2 ( msb) bit 1 otr vref avdd avss sense pin function descriptions pin number mnemonic description 1 clk clock input pin 2b it 12 least significant data bit (lsb) 3e12 bits 11e2 data output bit 13 bit 1 most significant data bit (msb) 14 otr out of range 15, 26 avdd 5 v analog supply 16, 25 avss analog ground 17 sense reference select 18 vref reference i/o 19 refcom reference common 20 capb noise reduction pin 21 capt noise reduction pin 22 cml common-mode level (midsupply) 23 vina analog input pin (+) 24 vinb analog input pin (e) 27 dvss digital ground 28 dvdd 3 v to 5 v digital supply definitions of specifications integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. zero error the major carry transition should occur for an analog value 1/2 lsb below vina = vinb. zero error is defined as the devia- tion of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (25 ) () (+ ) + + () = () () () ()
rev. e e6e ad9221/ad9223/ad9220 (avdd = 5 v, dvdd = 5 v, f sample = 1.5 msps, t a = 25
rev. e ad9221/ad9223/ad9220 e7e code 1.0 0.4 e0.6 0 4095 0.8 0.6 0.0 e0.4 0.2 e0.2 e0.8 e1.0 dnl e lsbs tpc 10. typical dnl frequency e mhz sinad e db 80 75 40 0.1 1.0 10.0 70 65 45 60 55 50 e0.5db e6.0db e20.0db tpc 13. sinad vs. input frequency (input span = 2.0 v p-p, v cm = 2.5 v) frequency e mhz thd e db e50 e55 e90 0.1 1.0 10.0 e60 e65 e85 e70 e75 e80 e20.0db e6.0db e0.5db e95 e100 tpc 16. thd vs. input frequency (input span = 5.0 v p-p, v cm = 2.5 v) code 1.0 0.4 e1.0 0 4095 0.8 0.6 0.0 e0.8 0.2 e0.6 e0.2 e0.4 0 inl e lsbs tpc 11. typical inl frequency e mhz thd e db e50 e55 e90 0.1 1.0 10.0 e60 e65 e85 e70 e75 e80 e20.0db e6.0db e0.5db e95 e100 tpc 14. thd vs. input frequency (input span = 2.0 v p-p, v cm = 2.5 v) sample rate e msps thd e db e60 e65 e100 0.4 0.8 4 e70 e75 e95 e80 e85 e90 0.6 1 2 3 5 6 5v p-p 2v p-p tpc 17. thd vs. sample rate (a in = e0.5 db, f in = 500 khz, v cm = 2.5 v) code hits 96,830 8,123,672 130,323 ne1 n n+1 tpc 12. grounded-input histogram (input span = 2 v p-p) frequency e mhz sinad e db 80 75 40 0.1 1.0 10.0 70 65 45 60 55 50 e0.5db e6.0db e20.0db tpc 15. sinad vs. input frequency (input span = 5.0 v p-p, v cm = 2.5 v) a in e dbfs 100 90 30 e60 e40 0 e20 70 60 40 50 80 snr/sfdr e db 20 10 e50 e30 e10 sfdr snr tpc 18. snr/sfdr vs. a in (input amplitude) (f in = 1.5 mhz, input span = 2 v p-p, v cm = 2.5 v) ad9223etypical performance characteristics (avdd = 5 v, dvdd = 5 v, f sample = 3.0 msps, t a = 25
rev. e e8e ad9221/ad9223/ad9220 ad9220etypical performance characteristics (avdd = 5 v, dvdd = 5 v, f sample = 10 msps, t a = 25
rev. e ad9221/ad9223/ad9220 e9e introduction the ad9221/ad9223/ad9220 are members of a high perfor- mance, complete single-supply 12-bit adc product family based on the same cmos pipelined architecture. the product family allows the system designer an upward or downward component selection path based on dynamic performance, sample rate, and power. the analog input range of the ad9221/ad9223/ad 9220 is highly flexible, allowing for both single-ended or differen- tial inputs of varying amplitudes that can be ac or dc coupled. each device shares the same interface options, pinout, and package offering. the ad9221/ad9223/ad9220 utilize a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (sha) implemented on a cost-effective cmos process. each stage of the pipeline, excluding the last stage, consists of a low resolution flash a/d connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash a/d. the pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. this means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. this latency is not a concern in most applications. the digital output, together with the out-of-range indicator (otr), is latched into an output buffer to drive the output pins. the output drivers can be configured to interface with 5 v or 3.3 v logic families. the ad9221/ad9223/ad9220 use both edges of the clock in their internal timing circuitry (see figure 1 and specifications for exact timing requirements). the a/d samples the analog input on the rising edge of the clock input. during the clock low time (between the falling edge and rising edge of the clock), the input sha is in the sample mode; during the clock high time, it is in hold. system disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input sha to acquire the wrong value, and should be minimized. the internal circuitry of both the input sha and individual pipeline stages of each member of the product family are opti- mized for both power dissipation and performance. an inherent trade-off exists between the input sha?s dynamic performance and its power dissipation. figures 2 and 3 show this trade-off by comparing the full-power bandwidth and settling time of the ad9221/ad9223/ad9220. both figures reveal that higher full- power bandwidths and faster settling times are achieved at the expense of an increase in power dissipation. similarly, a trade- off exists between the sampling rate and the power dissipated in each stage. as previously stated, the ad9221, ad9223, and ad9220 are similar in most aspects except for the specified sampling rate, power consumption, and dynamic performance. the product family is highly flexible, providing several different input ranges and interface options. as a result, many of the application issues and trade-offs associated with these resulting configurations are also similar. the data sheet is structured such that the designer can make an informed decision in selecting the proper a/d and optimizing its performance to fit the specific application. frequency e mhz 0 e3 e12 1 100 10 amplitude e db e6 e9 ad9221 ad9220 ad9223 figure 2. full-power bandwidth settling time e ns code 4000 3000 0 0 60 10 20 30 40 50 2000 1000 ad9220 ad9223 ad9221 figure 3. settling time analog input and reference overview figure 4, a simplified model of the ad9221/ad9223/ad9220, highlights the relationship between the analog inputs, vina, vinb, and the reference voltage, vref. like the voltage ap plied to the top of the resistor ladder in a flash a/d converter, the value vref defines the maximum input voltage to the a/d core. the minimum input voltage to the a/d core is automati- cally defined to be evref. v core vina vinb +v ref ev ref a/d core 12 ad9221/ad9223/ad9220 figure 4. ad9221/ad9223/ad9220 equivalent functional input circuit
rev. e e10e ad9221/ad9223/ad9220 the addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. the input stage allows the user to easily config- ure the inputs for either single-ended operation or differential operation. the a/d?s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. specifically, the input to the a/d core is the differ- ence of the voltages applied at the vina and vinb input pins. t herefore, the equation, vvinav inb core = () ? () << + << + () () () + () ( ) () ( ) ( ) = ( = = ) ( )
rev. e ad9221/ad9223/ad9220 e11e referring to figure 5, the differential sha is implemented using a switched-capacitor topology. therefore, its input impedance and its subsequent effects on the input drive source should be understood to maximize the converter?s performance. the com- bination of the pin capacitance, c pin , parasitic capacitance, c par , and sampling capacitance, c s , is typically less than 16 pf. when the sha goes into track mode, the input source must charge or discharge the voltage stored on c s to the new input voltage. this action of charging and discharging c s , averaged over a period of time and for a given sampling frequency, f s , makes the input impedance appear to have a benign resistive component. however, if this action is analyzed within a sampling period (i.e., t = 1/f s ), the input impedance is dynamic and there- fore certain precautions on the input drive source should be observed. the resistive component to the input impedance can be com- puted by calculating the average charge that gets drawn by c h from the input drive source. it can be shown that if c s is allowed to fully charge up to the input voltage before switches q s1 are opened, then the average current into the input is the same as if there were a resistor of 1/(c s f s ) ohms connected between the inputs. this means that the input impedance is inversely pro- portional to the converter?s sample rate. since c s is only 4 pf, this resistive component is typically much larger than that of the drive source (i.e., 25 k ? = ) ? ? ? () ( ) ? ? ( ) ? ?
rev. e e12e ad9221/ad9223/ad9220 shunt capacitor can help limit the wideband noise at the a/d?s input by forming a low-pass filter. note, however, that the combination of this series resistance with the equivalent input capacitance of the ad9221/ad9223/ad9220 should be evalu- ated for those time-domain applications that are sensitive to the input signal?s absolute settling time. in applications where har- monic distortion is not a primary concern, the series resistance may be selected in combination with the sha?s nominal 16 pf of input capacitance to set the filter?s 3 db cutoff frequency. a better method of reducing the noise bandwidth, while possi- bly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., vina and/or vinb) and analog ground. since this additional shunt capacitance combines with the equivalent input capacitance of the ad9221/ad9223/ad9220, a lower series resistance can be selected to establish the filter?s cutoff frequency while not de grading the distortion performance of the device. the shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, c h , further reducing current transients seen at the op amp?s output. the effect of this increased capacitive load on the op amp driv- ing the ad9221/ad9223/ad9220 should be evaluated. to optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. increasing the capacitance too much may adversely affect the op amp?s settling time, frequency response, and distortion performance. reference operation the ad9221/ad9223/ad9220 contain an on-board band gap reference that provides a pin-strappable option to generate either a 1 v or 2.5 v output. with the addition of two external resistors, the user can generate reference voltages other than 1 v and 2.5 v. another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. see table ii for a summary of the pin-strapping options for the ad9221/ad9223/ad9220 reference configurations. figure 9 shows a simplified model of the internal voltage refer ence of the ad9221/ad9223/ad9220. a pin-strappable reference amplifier buffers a 1 v fixed reference. the output from the reference amplifier, a1, appears on the vref pin. the voltage on the vref pin determines the full-scale input span of the a/ d. this input span equals, full-scale input span = 2 vref the voltage appearing at the vref pin as well as the state of the internal reference amplifier, a1, are determined by the volt- age appearing at the sense pin. the logic circuitry contains two comparators that monitor the voltage at the sense pin. the comparator with the lowest set point (approximately 0.3 v) controls the position of the switch within the feedback path of a1. if the sense pin is tied to refcom, the switch is connected to the internal resistor network, thus providing a vref of 2.5 v. if the sense pin is tied to the vref pin via a short or resistor, the switch is connected to the sense pin. a short will provide a vref of 1.0 v while an external resistor network will provide an alternative vref between 1.0 v and 2.5 v. the other comparator controls internal circuitry that will disable the reference amplifier if the sense pin is tied to avdd. disabling the reference amplifier allows the vref pin to be driven by an external voltage reference. a2 5k
rev. e ad9221/ad9223/ad9220 e13e table i. analog input configuration summary input input input range (v) figure connection coupling span (v) vina * vinb * no. comments single-ended dc 2 0 to 2 1 13, 14 best for stepped input response applica- tions, suboptimum thd, and noise performance. requires = + ( ) ( ) = + + ( ) + + ( )
rev. e e14e ad9221/ad9223/ad9220 driving the analog inputs introduction the ad9221/ad9223/ad9220 has a highly flexible input structure, allowing it to interface with single-ended or differen- tial input interface circuitry. the applications shown in sections driving the analog inputs and reference configurations, along with the information presented in input and reference over- view of this data sheet, give examples of both single-ended and differential operation. refer to tables i and ii for a list of the different possible input and reference configurations and their associated figures in the data sheet. the optimum mode of operation, analog input range, and asso- ciated interface circuitry will be determined by the particular application?s performance requirements as well as power supply options. for example, a dc coupled single-ended input would be appropriate for most data acquisition and imaging applications. also, many communication applications that require a dc coupled input for proper demodulation can take advantage of the excel- lent single-ended distortion performance of the ad9221/ad 9223/ ad9220. the input span should be configured such that the system?s performance objectives and the headroom requirements of the driving op amp are simultaneously met. alternatively, the differential mode of operation with a trans former coupled input provides the best thd and sfdr performance over a wide frequency range. this mode of operation should be considered for the most demanding spectral based applications that allow ac coupling (e.g., direct if to digital conversion). single-ended operation requires that vina be ac- or dc-coupled to the input signal source while vinb of the ad9221/ad9223/ ad9220 can be biased to the appropriate voltage corresponding to a midscale code transition. note that signal inversion may be easily accomplished by transposing vina and vinb. the rated specifications for the ad9221/ad9223/ad9220 are character- ized using single-ended circuitry with input spans of 5 v and 2 v as well as vinb = 2.5 v. differential operation requires that vina and vinb be simulta- neously driven with two equal signals that are in and out of phase versions of the input signal. differential operation of the ad9221/ad9223/ad9220 offers the following benefits: (1) signal swings are smaller and therefore linearity requirements placed on the input signal source may be easier to achieve, (2) signal swings are smaller and therefore may allow the use of op amps that may otherwise have been constrained by headroom frequencye mhz 20 70 90 0.1 100 1 cmr e db 10 80 40 60 50 30 ad9221 ad9223 ad9220 figure 11. ad9221/ad9223/ad9220 input cmr vs. input frequency limitations, (3) differential operation minimizes even-order harmonic products, and (4) differential operation offers noise immunity based on the device?s common-mode rejection. figure 11 depicts the common-mode rejection of the three devices. as is typical of most cmos devices, exceeding the supply limits will turn on internal parasitic diodes, resulting in transient cur- rents within the device. figure 12 shows a simple means of clamping an ac- or dc-coupled single-ended input with the addi tion of two series resistors and two diodes. an optional capaci- tor is shown for ac-coupled applications. note that a larger series resistor could be used to limit the fault current through d1 and d2 but should be evaluated since it can cause a degrada- tion in overall performance. a similar clamping circuit could also be used for each input if a differential input signal is being applied. table ii. reference configuration summary reference input span (vinaevinb) operating mode (v p-p) required vref (v) connect to internal 2 1 sense vref internal 5 2.5 sense refcom internal 2 = = ( + ) () ()
rev. e ad9221/ad9223/ad9220 e15e avdd ad9221/ ad9223/ ad9220 r s1 30 ( ) ? ? ( ) +
rev. e e16e ad9221/ad9223/ad9220 ac coupling and interface issues for applications where ac coupling is appropriate, the op amp?s output can be easily level shifted to the common-mode voltage, vcm, of the ad9221/ad9223/ad9220 via a coupling capaci tor. this has the advantage of allowing the op amp?s common-mode level to be symmetrically biased to its midsupply level (i.e., (v cc + v ee )/2). op amps that operate symmetrically with re spect to their power supplies typically provide the best ac performance as well as the greatest input/output span. thus, various high speed/performance amplifiers that are restricted to +5 v/e5 v operation and/or specified for 5 v single-supply operation can be easily configured for the 5 v or 2 v input span of the ad9221/ ad9223/ad9220. the best ac distortion performance is achieved when the a/d is configured for a 2 v input span and common- mode voltage of 2.5 v. note that differential transformer coupling, which is another form of ac coupling, should be considered for optimum ac performance. simple ac interface figure 15 shows a typical example of an ac-coupled, single- ended configuration. the bias voltage shifts the bipolar, ground-refer- enced input signal to approximately vref. the value for c1 and c2 will depend on the size of the resistor, r. the capaci tors, c1 and c2, are typically a 0.1 =+ () () + + ( ? ) =+ () () + + + = + < = + + < +
rev. e ad9221/ad9223/ad9220 e17e ad828: dual version of ad818 best applications: differential and/or low imped- ance input drivers, low noise, gains + + < = + ( ) = + ( < ) ( ) ( = = )
rev. e e18e ad9221/ad9223/ad9220 frequency e mhz e55 e95 1 100 10 sfdr e db e65 e75 e85 ad9221 ad9223 ad9220 figure 18. ad9221/ad9223/ad9220 sfdr vs. input frequency (v cm = 2.5 v, 2 v p-p input span, a in = e0.5 db) figure 19 shows the schematic of the suggested transformer circuit. the circuit uses a mini-circuits rf transformer, model #t4-6t, which has an impedance ratio of 4 (turns ratio of 2). the schematic assumes that the signal source has a 50 ? ? ? ( ) ( = = = )
rev. e ad9221/ad9223/ad9220 e19e shorting the vref pin directly to the sense pin places the internal reference amplifier in unity-gain mode and the resultant vref output is 1 v. therefore, the valid input range is 0 v to 2 v. however, shorting the sense pin directly to the refcom pin configures the internal reference amplifier for a gain of 2.5 and the resultant vref output is 2.5 v. thus, the valid input range becomes 0 v to 5 v. the vref pin should be bypassed to the refcom pin with a 10 + =+ () ? ? ? ?
rev. e e20e ad9221/ad9223/ad9220 the ad9221/ad9223/ad9220 contains an internal reference buffer, a2 (see figure 9), that simplifies the drive requirements of an external reference. the external reference must be able to drive a ? ( ) = + + ( ) + + + + + () ()
rev. e ad9221/ad9223/ad9220 e21e can be detected. table v is a truth table for the over/underrange circuit in figure 28, which uses nand gates. systems requiring programmable gain conditioning of the ad9221/ad9223/ ad9220 input signal can immediately detect an out-of-range condition, thus eliminating gain selection iterations. also, otr can be used for digital offset and gain calibration. table v. out-of-range truth table otr msb analog input is 00 in range 01 in range 10 underrange 11 overrange over = 1 under = 1 msb otr msb figure 28. overrange or underrange logic digital output driver considerations (dvdd) the ad9221, ad9223 and ad9220 output drivers can be configured to interface with 5 v or 3.3 v logic families by set ting dvdd to 5 v or 3.3 v respectively. the ad9221/ad9223/ ad9220 output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause glitches on the supplies and may affect sinad performance. applications requiring the ad9221/ ad9223/ad9220 to drive large capacitive loads or large fanout may require additional decoupling capacitors on dvdd. in extreme cases, external buffers or latches may be required. clock input and considerations the ad9221/ad9223/ad9220 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. the clock input must meet or exceed the minimum specified pulsewidth high and low (t ch and t cl ) specifications for the given a/d as defined in the switching specifications to meet the rated performance specifications. for example, the clock input to the ad9220 operating at 10 msps may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified t ch and t cl is 45 ns. for clock rates below 10 msps, the duty cycle may deviate from this range to the extent that both t ch and t cl are satisfied. all high speed high resolution a/ds are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency ( f in ) due to only aperture jitter ( t a ) can be calculated with the following equation: snr f t in a = [] ( )
rev. e e22e ad9221/ad9223/ad9220 clock frequency e mhz 300 240 12 power e mw 10 280 260 input = 5v p-p input = 2v p-p 220 200 8 6 4 2 014 figure 29c. ad9220 power consumption vs. clock frequency grounding and decoupling analog and digital grounding proper grounding is essential in any high speed, high resolution system. multilayer printed circuit boards (pcbs) are recom- mended to provide optimal grounding and power schemes. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation, and ground plane. these characteristics result in both a reduction of electro- magnetic interference (emi) and an overall improvement in performance. it is important to design a layout that prevents noise from cou- pling onto the input signal. digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. while the ad9221/ad9223/ad9220 fea tures separate analog and digital ground pins, it should be treated as an analog component. the avss and dvss pins must be joined together directly under the ad9221/ad9223/ad9220. a solid ground plane under the a/d is acceptable if the power and ground return currents are managed carefully. alterna tively, the ground plane under the a/d may contain serrations to steer currents in predictable directions where cross-coupling between analog and digital would otherwise be unavoidable. the ad9221/ ad9223/ad9220/eb ground layout, shown in figure 39, depicts the serrated type of arrangement. the analog and digital grounds are connected by a jumper below the a/d. analog and digital supply decoupling the ad9221/ad9223/ad9220 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. in general, avdd, the analog supply, should be decoupled to avss, the analog com mon, as close to the chip as physically possible. figure 30 shows the recommended decoupling for the analog supplies; 0.1 ( )
rev. e ad9221/ad9223/ad9220 e23e applications direct if down conversion using the ad9220 as previously noted, the ad9220?s performance in the differen- tial mode of operation extends well beyond its baseband region and into several nyquist zone regions. thus, the ad9220 may be well suited as a mix down converter in both narrow and wideband applications. various if frequencies exist over the frequency range in which the ad9220 maintains excellent dynamic performance (e.g., refer to figure 17 and 18). the if signal will be aliased to the adc?s baseband region due to the sampling process in a similar manner that a mixer will down- convert an if signal. for signals in various nyquist zones, the following equation may be used to determine the final frequency after aliasing. f 1 nyquist = f signal f 2 nyquist = f sample e f signal f 3 nyquist = abs (f sample e f signal ) f 4 nyquist = 2 = ( ) ( ) = = ( = = ) ( ) ( ) ( )
rev. e e24e ad9221/ad9223/ad9220 1.25k iout iout iout iout u () ( ) ( ) ( )
rev. e ad9221/ad9223/ad9220 e25e figure 36. evaluation board schematic r14 50
rev. e e26e ad9221/ad9223/ad9220 figure 37. evaluation board component side layout (not to scale) figure 38. evaluation board solder side layout (not to scale)
rev. e ad9221/ad9223/ad9220 e27e figure 39. evaluation board ground plane layout (not to scale) figure 40. evaluation board power plane layout
rev. e e28e ad9221/ad9223/ad9220 figure 41. evaluation board component side silkscreen (not to scale) figure 42. evaluation board component side silkscreen (not to scale)
rev. e ad9221/ad9223/ad9220 e29e outline dimensions 28-lead standard smwall outline package [soic] wide body (r-28) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.32 (0.0126) 0.23 (0.0091) 8
rev. e e30e ad9221/ad9223/ad9220 revision history location page 2/03?data sheet changed from rev. d to rev. e. updated graphic captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .g lobal changes to dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to digital output driver considerations (dvdd) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
e31e
c00576e0e2/03(e) printed in u.s.a. e32e

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